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may 2010 doc id 2424 rev 7 1/20 1 m48z08 m48z18 5 v, 64 kbit (8 kb x 8) zeropower ? sram features integrated, ultra low power sram and power- fail control circuit unlimited write cycles read cycle time equals write cycle time automatic power-fail chip deselect and write protection write protect voltages (v pfd = power-fail deselect voltage): ?m48z08: v cc = 4.75 to 5.5 v 4.5 v v pfd 4.75 v ?m48z18: v cc = 4.5 to 5.5 v 4.2 v v pfd 4.5 v self-contained batter y in the caphat? dip package pin and function compatible with jedec standard 8 k x 8 srams rohs compliant ? lead-free second level interconnect 2 8 1 pcdip28 (pc) battery caphat? www.st.com
contents m48z08, m48z18 2/20 doc id 2424 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m48z08, m48z18 list of tables doc id 2424 rev 7 3/20 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. pcdip28 ? 28-pin plastic dip, battery caphat?, package mech. data . . . . . . . . . . . . . 16 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures m48z08, m48z18 4/20 doc id 2424 rev 7 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. write enable controlled, write mode ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. chip enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. pcdip28 ? 28-pin plastic dip, battery caphat?, package outline . . . . . . . . . . . . . . . . . 16 figure 11. recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m48z08, m48z18 description doc id 2424 rev 7 5/20 1 description the m48z08/18 zeropower ? ram is an 8 k x 8 non-volatile static ram which is pin and function compatible with the ds1225. the monolithic chip provides a highly integrated battery-backed memory solution. the m48z08/18 is a non-volatile pin and function equivalent to any jedec standard 8 k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without an y requirement for special write timing or limit ations on the number of writes that can be performed. the 28-pin, 600 mil dip caphat? houses the m48z08/18 silic on with a long-life lithium button cell in a single package. figure 1. logic diagram table 1. signal names a0-a12 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally ai01022 13 a0-a12 w dq0-dq7 v cc m48z08 m48z18 g v ss 8 e
description m48z08, m48z18 6/20 doc id 2424 rev 7 figure 2. dip connections figure 3. block diagram a1 a0 dq0 a7 a4 a 3 a2 a6 a5 nc a10 a 8 a9 dq7 w a11 g e dq5 dq1 dq2 dq 3 v ss dq4 dq6 a12 nc v cc ai011 83 m4 8 z0 8 m4 8 z1 8 8 1 2 3 4 5 6 7 9 10 11 12 1 3 14 16 15 2 8 27 26 25 24 2 3 22 21 20 19 1 8 17 ai01 3 94 lithium cell v pfd v cc v ss voltage s en s e and s witching circuitry 8 k x 8 s ram array a0-a12 dq0-dq7 e w g power
m48z08, m48z18 operation modes doc id 2424 rev 7 7/20 2 operation modes the m48z08/18 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5 v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls below approximately 3 v, the control circuitry connects the battery which maintains data until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery backup switchover voltage. 2.1 read mode the m48z08/18 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be available at the da ta i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indete rminate state until t avqv . if the address inputs are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5 v or 4.5 to 5.5 v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) 1. see table 10 on page 15 for details. x x x high z cmos standby deselect v so (1) x x x high z battery backup mode
operation modes m48z08, m48z18 8/20 doc id 2424 rev 7 figure 4. read mode ac waveforms note: write enable (w ) = high. table 3. read mode ac characteristics 2.2 write mode the m48z08/18 is in the write mode whenever w and e are active. the start of a write is referenced from the latte r occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data- in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48z08/m48z18 unit min max t avav read cycle time 100 ns t avqv address valid to output valid 100 ns t elqv chip enable low to output valid 100 ns t glqv output enable low to output valid 50 ns t elqx (2) 2. c l = 30 pf. chip enable low to output transition 10 ns t glqx (2) output enable low to output transition 5 ns t ehqz (2) chip enable high to output hi-z 50 ns t ghqz (2) output enable high to output hi-z 40 ns t axqx address transition to output transition 5 ns ai01 38 5 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a12 e g dq0-dq7 valid
m48z08, m48z18 operation modes doc id 2424 rev 7 9/20 figure 5. write enable controlled, write mode ac waveform figure 6. chip enable controlled, write mode ac waveforms ai01 38 6 tavav twhax tdvwh data input a0-a12 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01 38 7b tavav tehax tdveh a0-a12 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
operation modes m48z08, m48z18 10/20 doc id 2424 rev 7 table 4. write mode ac characteristics 2.3 data retention mode with valid v cc applied, the m48z08/18 operates as a conventional bytewide? static ram. should the supply voltage decay, the ra m will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as ?don't care.? note: a power failure during a write cycle may corr upt data at the curren tly addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z08/18 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recommended. when v cc drops below v so , the control circuit switches power to the internal battery which preserves data. the internal button cell will maintain data in the m48z08/18 for an accumulated period of at least 11 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). e should be kept high as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to system stabilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48z08/m48z18 unit min max t avav write cycle time 100 ns t avwl address valid to write enable low 0 ns t avel address valid to chip enable 1 low 0 ns t wlwh write enable pulse width 80 ns t eleh chip enable low to chip enable 1 high 80 ns t whax write enable high to address transition 10 ns t ehax chip enable high to address transition 10 ns t dvwh input valid to write enable high 50 ns t dveh input valid to chip enable 1 high 30 ns t whdx write enable high to input transition 5 ns t ehdx chip enable high to input transition 5 ns t wlqz (2)(3) 2. c l = 30 pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. write enable low to output hi-z 50 ns t avwh address valid to write enable high 80 ns t aveh address valid to chip enable high 80 ns t whqx (2)(3) write enable high to output transition 10 ns
m48z08, m48z18 operation modes doc id 2424 rev 7 11/20 2.4 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 f (as shown in figure 7 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recommends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 7. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
maximum ratings m48z08, m48z18 12/20 doc id 2424 rev 7 3 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) ?40 to 85 c t sld (1) 1. soldering temperature of the ic l eads is to not exceed 260 c for 10 seconds. in order to protect the lithium battery, preheat temperatures must be limited such t hat the battery temperature does not exceed +85 c. furthermore, the devices shall not be exposed to ir reflow. lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
m48z08, m48z18 dc and ac parameters doc id 2424 rev 7 13/20 4 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 6. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 8. ac testing load circuit table 7. capacitance parameter m48z08 m48z18 unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 5 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance - 10 pf c io (3) 3. outputs deselected. input / output capacitance - 10 pf ai01398 5v out c l = 100pf or 30pf c l includes jig capacitance 1.8k device under test 1k
dc and ac parameters m48z08, m48z18 14/20 doc id 2424 rev 7 table 8. dc characteristics figure 9. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may perform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operati ons begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted min max unit i li input leakage current 0 v v in v cc 1 a i lo (2) 2. outputs deselected. output leakage current 0 v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e = v ih 3ma i cc2 supply current (standby) cmos e = v cc ? 0.2 v 3 ma v il input low voltage ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = ?1 ma 2.4 v ai00606 v cc input s (per control input) output s don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (m a x) v pfd (min) v s o
m48z08, m48z18 dc and ac parameters doc id 2424 rev 7 15/20 table 9. power down/up ac characteristics table 10. power down/up trip points dc characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). min max unit t pd e or w at v ih before power down 0 - s t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 - s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 - s t r v pfd (min) to v pfd (max) v cc rise time 0 - s t rb v ss to v pfd (min) v cc rise time 1 - s t rec e or w at v ih before power-up 2 - ms symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). min typ max unit v pfd power-fail deselect voltage m48z08 4.5 4.6 4.75 v m48z18 4.2 4.3 4.5 v v so battery backup switchover voltage 3.0 v t dr (3) 3. at 25 c, v cc = 0 v. expected data retention time 11 years
package mechanical data m48z08, m48z18 16/20 doc id 2424 rev 7 5 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark figure 10. pcdip28 ? 28-pin plastic dip, battery caphat?, package outline note: drawing is not to scale. table 11. pcdip28 ? 28-pin plastic dip, battery caphat?, package mech. data pcdip a2 a1 a l b1 b e1 d e n 1 c ea e 3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 33.02 1.3 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28
m48z08, m48z18 part numbering doc id 2424 rev 7 17/20 6 part numbering table 12. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m48z 08 ?100 pc 1 tr device type m48z supply voltage and write protect voltage 08 = v cc = 4.75 to 5.5 v; v pfd = 4.5 to 4.75 v 18 = v cc = 4.5 to 5.5 v; v pfd = 4.2 to 4.5 v speed ?100 = 100 ns package pc = pcdip28 temperature range 1 = 0 to 70 c shipping method blank = ecopack ? package, tubes tr = ecopack ? package, tape & reel
environmental information m48z08, m48z18 18/20 doc id 2424 rev 7 7 environmental information figure 11. recycling symbols this product contains a non-rechargeable lithi um (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. please refer to the following web site address for additional information regarding compliance statements and waste recycling. go to www.st.com/nvram , then select "lithium battery recycling" from "related topics".
m48z08, m48z18 revision history doc id 2424 rev 7 19/20 8 revision history table 13. document revision history date revision changes mar-1999 1 first issue 19-jul-2001 2 2-socket soh and 2-pin sh packages removed; reformatted; temperature information added to tables ( ta b l e 7 , 8 , 3 , 4 , 9 , 10 ) 19-dec-2001 2.1 remove all references to ?clock? 21-dec-2001 2.2 changes to text to reflect addition of m48z08y option 20-may-2002 2.3 modify reflow time and temperature footnotes ( ta bl e 5 ) 10-sep-2002 2.4 remove all references to ?snaphat? and m48z08y part ( figure 1 ; ta b l e 5 , 6 , 3 , 4 , 10 , 12 ) 01-apr-2003 3 v2.2 template applied; updated test condition ( ta b l e 1 0 ) 28-aug-2004 4 reformatted; removed references to ?crystal? (figure 1 ) 14-dec-2005 5 updated template, lead-free text, removed footnote ( ta b l e 8 , 12 ) 24-mar-2009 6 reformatted document; added text to section 5: package mechanical data ; added section 7: environmental information . 27-may-2010 7 updated section 3: maximum ratings , ta b l e 1 1 ; reformatted document; minor textual changes.
m48z08, m48z18 20/20 doc id 2424 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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